Minutes written by: A. Baudry, M. de Vos, S. Okumura

Approved by: A. Baudry, S. Okumura, 2000-10-30

Summary An informal meeting on European and Japanese correlator plans was held on 10 September 2000 in conjunction with the second face-to-face meeting of the ALMA Scientific Advisory Committee (ASAC) in Berkeley. Some technical issues of present plans were reviewed and similarity of enhanced technical and scientific goals were emphasized. Coordinated development and exchange of information will continue. It was recommended that interim reports should be prepared and near term actions were decided.

Japan: Y. Chikada, M. Ishiguro, S. Okumura

US: A. Wootten, J. Mangum (initially)

Correlator Issues and Timeline

Status of US, European and Japanese Correlators

High Speed Samplers Developments in Europe and Japan

Conclusions

1. Correlator Issues and Timeline

In addition to the ASAC and present meetings, the Baseline (NRAO), Future (Europe), FX (Japan) and Enhanced (tbd) correlator issues will further be discussed at the ALG meeting of 11 September 2000 and at the next ECC and ACC meetings of October in Paris.

NRAO will deliver the first quadrant (32 antennas, full polarization) of the Baseline correlator by mid-2004. As approved during the PDR of January 2000 in Charlottesville final commitment to the 64 antenna correlator should be made by 2003.

It is expected that interim reports from the European Future Correlator and Japanese FX correlator teams will be ready by the end of 2000. These reports will be used for another presentation at the next ASAC meeting (to be held in March 2001). Final reports of Phase1 activities are due at the end of 2001.

With Japan involved as the third partner in ALMA an Enhanced correlator will be required to handle a minimum of 78 antennas and the ALMA Compact Array; the definition of such a new correlator should be a joint effort of the European, Japanese, and US teams.

NRAO proceeds with detailed design and fabrication of subsystems of the Baseline Correlator. It is reminded that the NRAO design is for 2 bits, 4 levels. Each baseband input is 2 GHz or smaller (down to 62.5 MHz). There are 1024 channels per baseline at 4 GHz clock rate or with 4 baseband pairs 64 channels per 2 GHz baseband input and 4 polarization products. The number of channels can be traded against bandwidth and correlator products for polarization. The maximum number of antennas is 64.

The top level specifications and major features of the Future Correlator were presented at the ASAC meeting. Some features of the hybrid XF correlator are reminded below:

- 8 times 2 GHz baseband inputs

- large number of antennas ( > 64)

- large number of digital FIR filters (e.g. 16 FIRs per baseband)

- correlation 'plane' for each FIR with large number of channels

- correlation: 250/300 MHz clock rate, 4-bit format

- flexible allocation of channels with digital 'cross-bar' scheme

- FFT and sub-band concatenation

De Vos described the involvement of the Astron group in the project: architectural design, system simulations and requantization issues. Some initial chip development will be subcontracted to MIT/Haystack. It is intended to integrate prototyped elements in an experimental mock-up. Boards with generic building blocks are available (Astron). FIR filter prototypes will be developed at Bordeaux University.

FX Correlator

The Japanese plans were originally for the LMSA correlator and now for the enhanced ALMA. They include 256 k-point FFT in the F part of the system and correlation with flexible frequency-channel smoothing in the X part. Some characteristics are given below:

- bandwidth per IF = 4 GHz

- highest frequency resolution = 4 GHz / 128 000 = 31.25 kHz

- 2- or 3-bit correlation

- output channel number = 16 000 channels

- variable frequency resolution is possible with flexible smoothing (31.25 kHz unit)

- correlation for 4 IFs up to 80 antennas or so is possible

Okumura and Chikada explained that a pre-prototype correlator system for 2 GHz bandwidth will be made in 2001 for an 128 k FX correlator with two F blocks and one X block; 512-point FFT LSIs in the F block and discrete chips in the X block will be clocked at 64 MHz.

The memory required in the FX correlator mainly goes to the X part (about 80%); this has been well reduced (25%) in the new Japanese plan which implemented flexible smoothing and short-term buffering method

thus implying lower cost.

Chikada introduced an alternative architecture where the F block is reconfigured by doing an inverse transform after the first FFT stage.

Similarity of European and Japanese Plans

The European digital hybrid correlator bears some resemblance to the Japanese FX correlator the FFT being equivalent to FIR filtering. In both projects the goals are similar: achieve wider band correlation, higher spectral resolution and better sensitivity than in the present baseline correlator plan. Therefore, together with high configuration flexibility, enhanced scientific performances are expected from the future correlator plans. However, the cost is still uncertain.

3. High Speed Sampler (HSS) Developments in Europe and Japan

HSS developments in Europe

Baudry made a brief report on recent work and status at the time of the meeting.

A comparator clocked at 2 GHz, an input amplifier/adaptator with 1.2 GHz bandwidth, and a complete 2-bit sampler (input amplifier loaded with two comparators) were designed in HCMOS7 technology from STM. The layouts have been sent by IXL and Observatoire de Bordeaux to the foundry for ASIC production. Return from the foundry is expected in October.

A shift to SiGe fast technology from STM has been prepared, and their design kit has been installed. There is now full agreement with STM to submit future SiGe BiCMOS ASIC designs. A first run with appropriate layout verification will be prepared for early November this year. Other runs will be possible in December and early next year for 8-level comparators.

There has been good progress on the test bench for prototype samplers. This is a simplified correlator (16 lags) comprising an adjustable clock generator and a stabilized 0 to 4 GHz input noise source. Samplers up to 4 bits can be tested. The bench will provide dynamic characterization of the prototype samplers fabricated in Europe or elsewhere.

HSS developments in Japan

Okumura reported on Japanese 8 Gsps, 1-bit digitizer experiments and future plans.

The existing 1-bit GaAs digitizer clocked at 8 GHz (700 mV peak-to-peak) with analog input bandwidth in the range 1 to 2 GHz (200-400 mV pp) was connected to the XF correlator input of the Nobeyama Mm array. Input power linearity measurements and DC offset were obtained from auto-correlation spectra. Results of August and early September show satisfactory passband characteristics (BW = 1 GHz) at this stage.

A second digitizer similar to that used in the above experiments was fabricated in June. It could be used for cross-correlation of noise spectra.

Future work will include pre-prototyping an 4 Gsps, 2-bit ADC from OKI GaAS chips, and measuring the sampling jitter and width of the indecision region for existing digitizers. Elaborate tests should be feasible on the simplified test correlator dedicated to prototype samplers (see Actions below).

4. Conclusions

• It was agreed that the European Future Correlator and Japanese FX Correlator teams will continue their feasibility and prototype design studies in parallel. The teams will keep each other well informed and give mutual feedback throughout Phase 1.

• Each group wil continue their work with the following common specifications:

- eight 2 GHz basebands (4 bands with 2 polarizations each)

- variable frequency resolution

- highest spectral resolution of order 5 kHz

- 78x78 correlations (main array) + 16x16 correlations (ALMA Compact Array) are required; no need for all cross-correlations between any 12-m and any 6-m antennas

- high configuration flexibility with minimum number of sub-arrays = 4

• Interim reports from the European Future Correlator and Japanese FX correlator teams wil be prepared by the end of 2000.

• It was agreed that each group should provide first estimates of performance, cost and power consumption by early 2001.

• It was agreed that selection of a common concept for the Enhanced Correlator would require joint US-Europe-Japan discussions. It is importantthat the choice of the architecture of this new correlator is driven by scientific requirements from the ALMA project.

• de Vos to work with the ALMA Computing and Software division (Glendenning and Raffi) to assess the impact of various correlator designs on the computing and software sub-systems and the interface requirements (*)

• European and Japanese correlator teams to summarize jointly the interface requirements of the Enhanced Correlator to the ALMA Computing and Software division

• Baudry and Okumura to investigate with IRAM the modifications to the sampler test correlator that are needed to test the Japanese sampler(*)

• Baudry to inform Okumura on power consumption in ASIC FIRs.

• Baudry and Okumura to distribute these minutes.

(* action also in minutes of the ALMA Liaison Group, 11 September 2000 )