Dear ASAC members,

Attached you find a preliminary report on  "Cost reduction in FX correlator
for enhanced ALMA and sensitivity consideration" by Japanese
correlator working group to ASAC. This report is the revised version of
the report to the recent ALG meeting. We are sorry
for that this is sent to you just before the today's telecon.
Someone will have a problem in reading it, then
the text file is attached below this mail (except for a figure).

If needed, please transfer it to persons
who are related to or interested in this issues.

Sincerely Yours,

Ryohei Kawabe

----------------------------------------------------------------------
Cost reduction in FX correlator for enhanced ALMA and sensitivity
consideration

                               2000.7.10 S.K.Okumura, Y.Chikada and M.Momose

<<Enhanced-ALMA FX correlator>>
     There were discussions whether it is appropriate or not to have
 the FX correlator capability of 128k channel/IF, considering the
costs of the correlator itself and the post-process computing.
Thus we have started to discuss several possibilities to reduce
the correlator cost conserving almost all of the scientific merits
we proposed. We are now considering the reduction of the output
channel number from 128k/IF to 32K or 16K /IF through flexible
smoothing operation. This will eliminate the fear that the large amount
of the frequency channels might increase the costs of post-detection
computing and archiving. We estimate that the total cost of the FX
correlator becomes at least half due to the change(s) below. Now we
are discussing the detailed hardware design and the precise amount
 of the cost reduction. We are happy to report the concrete plans
 under the technical discussions now.
We are studying the possibilities to reduce the costs, maintaining
the total bandwidth of 16GHz and the minimum frequency resolution
of 32kHz simultaneously.　(1). We found a method where we can replace
 the 'short-term' integration memory in the X-part ASIC to a simple
 register if we have a 'short-term' spectrum buffer at the output of
the F-part (FFT). ( See attached figure. ) The spectrum buffer accepts
 inputs, e.g., 0,1,2,3,...,n (-th) frequency channels successively as the
FFT
 goes, stores them M times (i.e. M segments) in different addresses,
and outputs such that the identical frequency channels be output
successively, e.g., 0,0,0,...0,1,1,1,...1, 2,...,n. The unit price per bit
of
the ASIC 'short-term' integration memory is two orders of magnitude
expensive compared to that of the off-the-shelf memory chip needed
for the 'short-term' spectrum buffer. As a result, we can expect a
99% cost reduction in 'short-term' integration memory which
consists 80% costs in the conventional X-part which were 80%
of the total costs of the FX.

                    Conventional FX     Present Plan
    F-part costs     20%                < 20 + 1 %
    X-part costs     16 + 64=80%          16 + 1=17%
        SIM(*)          (64%)             (1%)
    total costs     100%                < 38%

In this method, essentially, correlator cost reduction can be realized
without frequency region bunching. However, for the convenience of
the further processing in the computers, flexible smoothing function
will be implemented at the output of the correlator.


(2). Another method is to have frequency region bunching – either
smoothing　or frequency baseline calculation -- just after the
cross-correlation multipliers to reduce the number of word number
 of the 'short-term' integration memory. In this latter method,
there might be some restriction in the selection of the frequency
baseline region.

Only for the millimeter-wave observations, we will lose some
amount of the efficiency of imaging line survey over the whole
4GHzBW/IF and the possibility to make serendipitous observations
 through the frequency region bunching. However, for continuum
and the line emission we know, nothing will be lost, and for
 the sub-mm observations, we are able to proceed
the wide-band( >1000km/s) and high-resolution( < 0.1 km/s )
observations simultaneously. So the FX correlator still have
much more scientific merits compared to the baseline-ALMA XF correlator.

<<Considerations on sensitivity>>
 There are some arguments on the sensitivity losses by
 the FX architecture. One is on the additive noises that
 arise in the finite-length arithmetic in the FFT. We can
and will choose the word-length to satisfy the condition
that those noises be negligibly small compared to those of ADC’s.
Furthermore, FX has capability of accommodating multi-bit ADC’s
even 6-8 bit ones such as commercially available ADC’s  which are
 in the market for 1 GHz uses. This implies that FX could be more
sensitive in the near future.
The other is on the algorithmic problem. If there is no FFT segment
overlapping, there is some loss of correlation samples in the large lag
portion of the correlation function. This is true. But this causes no
harm in continuum observations and very small harm in the cases
where the frequency binding-up is executed. If there are anyone
who are not contended with the sensitivity in the highest frequency
resolution, we can even double the number of FFT channels at
 a negligibly small cost increase to realize binding-up for those
observations.

<<next-generation correlator meeting>>
In order to discuss the specifications and designs of the next-generation
correlator, Japanese correlator group would propose the correlator
technical meeting in Tokyo at the end of August or September.
The tentative contents are :
   #Necessary specifications for the next-generation correlator
( Science, System, ... )
   #Japanese proposal and status
   #European proposal and status
   #Comments from the baseline-ALMA correlaror(?)
   #Discussion for possible collaborations
If possible,
  ##progress reports of the collaboration with HSS for baseline-ALMA
    -Japan
    -Europe

If the outline of this meeting is confirmed at ALG, we would like
to negotiate the date, contents and speakers etc to
the European and U.S. correlator people.

Appendix:Europe-Japan Meeting on High Speed Digitizer
Development Plans and Tests on 30 March 2000 11:00-13:
( A. Baudry, S.K.Okumura, and R. Kurz @ ESO,Garching )

  1) Introduction of Japanese development plan with OKI/NRO sampler and
Technical discussion
        # OKI chips
        # 1-bit experiments using OKI chips @8Gsps
                  => measurements of fundamental parameters
                  (sampling jitter, DC offset, and width of the indecision
region)
        # development of 2-bit ADC@4Gsps
                  => Technical problem : Integration of sampling circuit,
etc...
2) Introduction of European development plan and test, and
     Technical discussion
        # high speed comparator with advanced CMOS technology and at a later
          stage with SiGe technology (year 2001)
                  => comparison of technical problems with different
technologies
        # integration of the input analog amplifier on ASIC.
        # fabrication of test correlator for 4GHz-clock sampling devices
3)Cooperation and mutual information
       ##Exchange information about the results of the tests and/or
         fabrication by June-July 2000 and at a later date when intermediate
         or complete results become available.
         Around July 2000: Japan will have almost finished the 1-bit
experiments,　
Europe will have fabricated a first comparator at less than
 4 GHz　clock sampling, and will have started developing
the test correlator.
       ##attendance on  Interim Design Review of ALMA HSS pre-prototype with
Europe
 and Japan. A tentative date for the interim review is the end of January
 2001.
       ##Performance tests using European test correlator for both high
speed
digitizers( Japan and Europe ) around mid-June 2001.

  @It was recognized that having different chip technologies based on
 advanced CMOS and SiGe in Europe and GaAs in Japan is of interest to ALMA.