One of the challenges of building a full-sampling array feed for radio astronomy is the large signal processing requirement. There are three general categories of signal processors: analog signal phasing and addition, digital phasing and summation, and digital cross-correlation followed by phasing and summation. The first method may be most suitable for a very wideband continuum receiver for which the signal processing speeds are not economically feasible with current digital technology. This note focuses on the latter two methods. Signal processing loads, in arithmetic operations per second, are given here for a number of example array sizes.
Direct beamforming is the weighted voltage vector sum of signals from adjacent elements in the feed array to form an efficient signal output for a chosen direction in the reflector antenna's far field. The signal operations are shown in Figure 1. The weights, Wxx, are vector rotations and amplitude scalings whose arithmetic involves four multiplies and two additions. Since most signal processoring chips do both adds and multiplies in one clock cycle we will give them a common name, "operation", abbreviated "Op" in the figure. Each array element signal can be used in a number of different beams, but each signal requires a different weight for each beam.
The number of elements needed to form one beam depends on the antenna efficiency required. The minimum number is typically 7, but 19 gives a somewhat higher efficiency at the expense of a greater signal processing load. The number of beams that can be formed depends on the total size of the array. For a short focal ratio reflector (F/D < 0.5) the number of beams can be roughly as large as the number of elements, if only 7 elements are required per beam.
An expression for the beamforming signal processing load, in operations per second, is given near the bottom of Figure 1. Some example numbers are given in Table 1. The quantity, (BW), is the receiver's IF bandwidth in Hz, which is the same as the complex digitizer speed in samples per second.
Most radio astronomy applications require a spectrometer so an FFT engine is shown attached each beam output. An expression for the FFTs signal processing load is given at the bottom of Figure 1.
Another direct beamforming configuration is to put the FFT engines at the outputs of the array elements, as shown in Figure 2. This has the advantage of allowing the signal weights, W, to be a function of frequency, which can be used to compensate for different amplifier, filter, and antenna characteristics on each element. This requires more FFT engines if the number of elements is greater than the number of beams formed as can be seen by comparing the expressions at the bottoms of Figures 1 and 2. It also requires more memory for the storage of weights, but this is probably a very small penalty. Note, however, that the processing speed requirement remains the same on the weight and summation modules since the input and output data rates of an FFT are equal.
Some numerical examples of signal processing requirements for the direct beamforming method shown in Figure 2 are given in Table 1. Note that the FFTs tend to dominate the processing costs so some consideration needs to be given to whether frequency-dependent element signal weights are required. The two cases marked with dashes are for arrays that might be designed for the express purpose of correcting for large scale reflector aberrations, such as astigmatism, where only one beam output is needed. For these two examples we have assumed that only 32 frequency resolution channels are required for accurate array phasing.
The last two columns show estimates of the number of signal processing DSP or FPGA chips that are required to handle a one MHz IF bandwidth with current technology. The number of chips will scale linearly with bandwidth. Details of interconnects and parallel processing efficiency remain to be considered. A 30% efficiency factor has been assumed since the published efficiency of an FFT in one of the chip spec sheets was about 60%. An FPGA will be less adaptable to different array configurations and applications.
The basic cross-correlation signal processing components are shown in Figure 3. One advantage of the cross-correlation method is that the weights used to for different beams may be changed after the data have been stored on permanent media. Hence, various weights may be tried in an optimization procedure to obtain the greatest signal to noise or antenna sidelobe characteristics. A major drawback of cross-correlation is that the voltage domain signal is not available for use of the reflector antenna in a synthesis array.
In Figure 3 each multiplier involves four arithmetic multiplies and two adds, and the accumulator requires two adds for a total of eight operations per data sample interval. We assume here that the accumulators will integrate for many data sample intervals so that the subsequent data processing speed will be negligible. If all possible cross- and self-correlations for an array are computed, the processing requirement is given by the expression at the bottom of Figure 3. However, correlations between distant elements in the array may be of little value so that the practical requirement will be considerably less than this for large arrays. Hence, this expression gives an upper limit to the number of operations per second. The exact number will depend on the number of elements used to form each beam.
Anyone familiar with radio astronomy correlators will recognize that the cross correlations can be performed much less expensively with one- or two-bit multipliers when the signals are primarily broadband noise. The multi-bit arithmetic implied in Figure 3 offers a wide dynamic range to RFI, but it may not be required in many cases.
A spectral line version of the correlation array feed processor is shown in Figure 4. In this case the FFT engines must be placed in each array element's signal line since the outputs of the correlators are in the power domain rather than the voltage domain as is the case with direct beamforming in Figure 1. An FFT must use multi-bit input and internal arithmetic, but its outputs can be trimmed to any number of bits as permitted by the dynamic range needed. The addition of FFTs does not increase the processing speed requirements of the correlators for the same total bandwidth, but the number of two-bit multipliers and accumulators would grow linearly with the number of channels. The operations per second for the FFT stage and multi-bit correlators are given by the two expressions at the bottom of Figure 4.
An alternative spectral line configuration would be to use multi-lag correlators and matching accumulators. This is a viable prospect for one or two-bit correlators but would be prohibitively expensive for multi-bit correlators. When two-bit correlators are acceptable we will need to look at the details of a particular implementation to see whether the FFT or multi-lag correlator is more economical. The number of FFT engines increases linearly with the number of array elements while the number of multi-lag correlators increases nearly as the square of the number of elements. Also, the multi-lag correlator size increases linearly with the number of frequency channels while the FFT size increases only as the log of the number of channels.
Table 2 shows the signal processing speed requirements for a number of array sizes and two spectrum lengths for the spectral line configuration shown in Figure 4. Note that the numbers in the third, fifth, and sixth columns are upper limits since correlations of widely spaced elements are included. The correlation numbers will probably come down by factors of two to four for the largest array sizes shown. Note that the processing requirements are dominated by the correlators for all but the smallest array or very large numbers of frequency channels.
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